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Home  /  Integrated Circuits (ICs)  /  Embedded - CPLDs (Complex Programmable Logic Devices)  /  Altera EP900JM

EP900JM

Active Icon Active - IC CPLD 24MC 55NS 40JLCC
EP900JM
EP900JM
Altera
Manufacturer:
Mfr Part #
Datasheet:
Description:
IC CPLD 24MC 55NS 40JLCC
 
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EP900JM Specification

Product Attribute
Attribute Value
Manufacturer
Series
-
Packaging
Bulk
Product Status
Active
Programmable
Not Verified
Programmable Type
EPLD
Delay Time tpd(1) Max
55 ns
Voltage Supply - Internal
4.5V ~ 5.5V
Number of Logic Elements/Blocks
-
Number of Macrocells
24
Number of Gates
-
Number of I/O
24
Operating Temperature
-55 ℃ ~ 125 ℃ (TC)
Mounting Type
Surface Mount
Package / Case
40-CLCC Window (J-Lead)
Supplier Device Package
40-JLCC

EP900JM Description

## Device Overview

The Altera EP900JM is a member of the MAX 9000 series Complex Programmable Logic Devices (CPLDs), designed for moderate-to-high complexity logic applications requiring fast, deterministic timing and non-volatile configuration. Fabricated using advanced CMOS technology, the device delivers low power consumption, high-speed pin-to-pin operation, and robust I/O flexibility. It is suitable for control signal routing, bus interfacing, glue logic, and small-scale arithmetic functions in embedded, industrial, and communication systems.

## Logic Architecture

The EP900JM contains 900 macrocells, organized into logic array blocks (LABs) for optimal placement and routing. Each LAB comprises 60 macrocells, and each macrocell integrates a 16-input combinational logic array, a flip-flop for sequential logic, and dedicated carry logic. The architecture supports efficient implementation of arithmetic functions, counters, adders, and state machines, enabling high-speed operation with minimal propagation delay. Its deterministic architecture ensures predictable timing across synchronous systems.

## Timing and Performance

With a speed grade of -12, EP900JM is optimized for fast combinational and sequential logic operation. Typical pin-to-pin propagation delays are in the range of a few nanoseconds. Dedicated carry chains reduce delay for arithmetic functions such as counters and adders, enabling high-speed arithmetic and combinational logic. The predictable timing characteristics make the device suitable for deterministic control, bus interfacing, and address decoding applications.

## I/O and Package

EP900JM is available in a 100-pin Thin Quad Flat Package (TQFP), offering flexible access to user I/Os. It supports multiple voltage standards, including TTL and LVCMOS, providing compatibility with various logic families. Input pins include hysteresis for improved noise immunity, while output pins provide programmable drive strength and slew-rate control. Individual I/O configuration supports mixed-voltage interfacing and low-power operation, making the device suitable for embedded and industrial systems.

## Power Consumption

The device features low static and dynamic power consumption due to its CMOS architecture. Typical operating voltage is 3.3 V, with optional support for lower voltage operation depending on system requirements. Efficient macrocell utilization and optimized fan-out design reduce dynamic power. The ability to selectively power down unused LABs further minimizes overall power consumption, making it suitable for thermally constrained or battery-operated systems.

## Configuration and Programming

EP900JM is a one-time programmable (OTP) CPLD, providing non-volatile configuration that persists across power cycles. Programming is performed using Altera MAX+PLUS II or Quartus II software, which generates a fuse map defining the logic functions and I/O behavior. The OTP architecture eliminates the need for external configuration memory while providing immediate availability of logic at power-up. The device also supports JTAG programming for in-system verification and testing.

## Reliability and Operating Conditions

The EP900JM is rated for commercial and industrial temperature ranges, with industrial operation from -40°C to 85°C. It includes ESD protection, latch-up immunity, and robust configuration memory stability. Deterministic propagation delays ensure reliable performance for control signals, counters, and state machines. Non-volatile configuration ensures predictable startup behavior for industrial, embedded, and communication applications.

## Applications

Typical applications include bus interfacing, address decoding, glue logic for microprocessor systems, signal multiplexing and demultiplexing, control and timing signal generation, counters, comparators, and small-scale arithmetic operations. The combination of high-speed pin-to-pin performance, flexible I/O, low power consumption, and non-volatile configuration makes EP900JM suitable for embedded control systems, industrial automation, instrumentation, telecommunications, and other applications requiring deterministic, reliable programmable logic.

EP900JM Stock: 25720

History Price
$26.92000
Certificates
5.0 / 5.0
review stars
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Jukka Laakso
Location Icon Finland
5 stars
2021-12-03 00:22
I order 10pcs. Now test three chips and two was ID 0x441, wich is STM32F412, not STM32F407. I am wery disapointed.
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Kęstutis Darius
Location Icon Lithuania
5 stars
2021-12-27 06:22
The goods are very satisfied, the seller Thank you very much.
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Justine Perrin
Location Icon France
5 stars
2021-06-10 07:32
Recu in 89 days, strip, to test
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Lotte van der Veen
Location Icon Netherlands
5 stars
2021-11-23 06:50
All ok, thank you!
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Hugo
Location Icon Spain
5 stars
2021-12-23 03:52
All right. Received within time

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